Image shown is for reference only. Actual package may vary. Refer to the product data sheet for package details.
X2-DFN0808-4.png
Image shown is for reference only. Actual package may vary. Refer to the product data sheet for package details.
X2-DFN1010-6.png
Image shown is for reference only. Actual package may vary. Refer to the product data sheet for package details.
X2-DFN1410-6.pngSingle Buffer, Open Drain
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The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G07 is a single buffer gate with an open drain output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
| Function | Buffer |
|---|---|
| Type | Buffers/Inverters/Transceivers |
| Compliance (Only Automotive supports PPAP) | Standard |
| Channels | 1 |
| Family | AUP |
| VCC Min (V) | 0.8 |
| VCC Max (V) | 3.6 |
| Input Type | Standard CMOS |
| Output Type | Open-Drain |
| Output Current (mA) | 4 |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2299 | 2018-03-01 | 2018-06-01 | Additional Qualified (A/T) Assembly Test Site |
