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SO-8.pngCOMPLEMENTARY PAIR ENHANCEMENT MODE MOSFET
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This new generation MOSFET has been designed to minimize the onstate resistance (RDS(ON)) and yet maintain superior switching performance, making it ideal for high efficiency power management applications.
| AEC Qualified | Yes |
|---|---|
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
| Polarity | N+P |
| ESD Diodes (Y|N) | No |
| |VDS| (V) | 40, 40 V |
| |VGS| (±V) | 20, 20 ±V |
| |IDS| @TA = +25°C (A) | 6.9, 5.1 |
| PD @TA = +25°C (W) | 1.8 |
| RDS(ON)Max@ VGS(10V)(mΩ) | 24, 45 mΩ |
| RDS(ON)Max@ VGS(4.5V)(mΩ) | 32, 55 mΩ |
| |VGS(TH)| Max (V) | 2.4, 2.2 V |
| QG Typ @ |VGS| = 4.5V (nC) | 8.8, 10.6 nC |
| QG Typ @ |VGS| = 10V (nC) | 19.1, 21.5 nC |
| CISS Typ (pF) | 1060, 1154 pF |
| CISS Condition @|VDS| (V) | 20, 20 V |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2495 | 2021-03-31 | 2021-07-01 | Qualification of Additional Assembly & Test Sites and Additional Wafer Back Grinding and Back Metal Process Source for Select Discrete Products |
| PCN-2403 | 2019-03-25 | 2019-06-19 | Qualification of Additional Wafer Solderable Front Metal Plating, Back Grinding and Back Metal Process Source, Additional Wafer Source, or Additional Assembly and Test site for Select Products. |
