Wide Range 3.0V-5.5V PLL Clock Multiplier
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This Clock Multiplier is the most cost-effective way to generate a high quality, high frequency clock outputs from lower frequency crystal or clock input. It is designed to replace crystal oscillators in most electronic systems, clock multipliers and frequency translation devices with low output jitter. The device implements a standard fundamental mode using PLL techniques and inexpensive crystal to produce output clocks up to 200 MHz.
The internal Logic divider is to generate nine different popular multiplication factors, allowing one chip to output many common frequencies.
9 selectable frequencies controlled by S0, S1 pins
Operating voltages of 3.0 to 5.5V
Lead free SOIC-8 package
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 3.3, 5 |
| Additive Jitter (ps) | 120 |
| Skew (PS) | 0 |
| Maximum Output Frequency (MHz) | 200 |
| Input Type(s) | Crystal, LVTTL, LVCMOS |
| Output Type(s) | LVCMOS |
| Number of Outputs | 2 |
| Function | Generator |
| Ambient or Junction Temperature (°C) | -40 to 85 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2594 | 2022-08-31 | 2023-02-28 | Device End of Life (EOL) |
| PCN-2293 | 2018-01-16 | 2018-01-16 | Fab Transfer for PT7C4512WE and PT7C4512WEX Devices Due to Current Fab Closure |
