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The AZ4052 is high-speed si-gate CMOS device. The AZ4052 is dual 4-channel analog multiplexer or demultiplexers with common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E =LOW, one of the four switches is selected (Low-impedance On-state) with pins S0 and S1. When pin E =HIGH, all switches are in the high-impedance Off-state, independent of pins S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E). The VCC to GND ranges are 3.0V to 10V. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC-VEE may not exceed 10V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (Typically Ground).
• Wide Operation Voltage: ±5.0V or 10V • Low On-resistance: - 55Ω (Typ.) at VCC-VEE=5V - 40Ω ( Typ.) at VCC-VEE=10V • Ultra Low THD+N: 0.003% @ 10V, 0.008% @ 5.0V • Ultra Low Crosstalk: -120dB • Ultra Low Noise: 6.0μVRMS • Operating Temperature: -40°C to 85°C
| Family | CMOS |
|---|---|
| Description | Dual 1 to 4 Channel Multiplexer |
| Maximum Switch Leakage | ±2 |
| RON (Typical) | 65 |
| RON Flatness Max | 18 |
| RON Mismatch Max | 6 |
| Switch Enable Time Max @ 5.0V | 81 |
| VCC Maximum Rating | 10 |
| VCC Min (V) | 3 |
