PI4MSD5V9543B

Description

The PI4MSD5V9543B is a bidirectional translating switch, controlled by the I2C bus. The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any individual SCx/SDx channels or combination of channels can be selected, determined by the contents of the programmable control register. Two interrupt inputs, INT0 and INT1, one for each of the downstream pairs, are provided. One interrupt output, INT, which acts as an AND of the two interrupt inputs, is provided.

An active LOW reset input allows the PI4MSD5V9543B to recover from a situation where one of the downstream buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C bus state machine and causes all the channels to be deselected, as does the internal power-on reset function.

The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage which will be passed by the PI4MSD5V9543X. This allows the use of different bus voltages on each SCx/SDx pair, so that 1.2V,1.8 V, 2.5 V, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.

The PI4MSD5V9543A and PI4MSD5V9543B are identical except for the fixed portion of the slave address.

Feature(s)

• 1-of-2 bidirectional translating multiplexer
• I2C-bus interface logic
• Operating power supply voltage:1.65 V to 5.5 V
• Allows voltage level translation between 1.2V, 1.8V,2.5 V, 3.3 V and 5 V buses
• Low standby current
• Low Ron switches
• Channel selection via I2C bus
• Power-up with all multiplexer channels deselected
• Capacitance isolation when channel disabled
• No glitch on power-up
• Supports hot insertion
• 5 V tolerant inputs
• 0 Hz to 400 kHz clock frequency
• ESD protection exceeds 8000 V HBM per JESD22- A114, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: SOIC-14W, TSSOP-14L