1:4 Clock Driver for Intel PCIe® 3.0 Chipsets
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The PI6C20400B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compatible with PCIe 1.0 and 2.0 specification.
The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is low, the output clocks are Tristated. When PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated.
Compliance (Only Automotive(Q) supports PPAP) | Standard |
---|---|
Function | PCIe clock buffer |
Number of Outputs | 4 |
Output Type(s) | HCSL |
Maximum Output Frequency (MHz) | 100 |
Additive Jitter (ps) | 50 |
Supply Voltage (V) | 3.3 |
Input Type(s) | HCSL |
Skew (PS) | 50 |
Ambient or Junction Temperature (°C) | -40 to 85 |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
PCN # | Issue Date | Implementation Date | Subject |
---|---|---|---|
PCN-2487 | 2020-10-07 | 2021-01-07 | Fab Porting from Global Foundries to Magnachip, Assembly & Test Site Transfer, and Datasheet Change |
PCN-2481 | 2020-08-26 | 2021-02-26 | Device End of Life (EOL) |
PCN-2325 – Rev 3 (Interim Update) | 2018-04-20 | 2020-11-20 | Fab Porting from Global Foundries to MagnaChip |