Very Low Power 2-Output PCIe Gen 4 Clock Buffer
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It uses Diodes' proprietary PLL design to achieve very low jitter that meets PCIe Gen1/Gen2/Gen3/Gen4 requirements. Other than PCIe 100MHz support, this device also support Ethernet application with 50MHz or 125MHz via SMBus. It provides various options such as different slew rate and amplitude through strapping pins or SMBUS so that users can configure the device easily to get the optimized performance for their individual boards.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Function | PCIe clock buffer |
| Number of Outputs | 2 |
| Output Type(s) | LP-HCSL |
| Maximum Output Frequency (MHz) | 125 |
| Additive Jitter (ps) | 0.1 |
| Supply Voltage (V) | 1.8 |
| Input Type(s) | HCSL |
| Skew (PS) | 50 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2328 | 2018-04-12 | 2018-10-12 | Device End of Life for tray packaging only |
