Low Power 2-Output PCIe 5.0 Clock Buffer With On-Chip Termination to support Zout=100 Ohm
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The PI6CB33201 is a two-output very-low-power PCIe Gen1/ Gen2/Gen3/Gen4/Gen5 clock buffer. It takes a reference input to
fanout two 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save eight
external resistors and make layout easier. Individual OE pin for each output provides easier power management.
It uses Diodes proprietary PLL design to achieve very-low jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 requirements.
Other than PCIe 100MHz support, this device also support Ethernet application with 50MHz, 125MHz, and 133.33MHz via
SMBus. It provides various options such as different slew rate and amplitude through SMBUS, so users can configure the device easily to get the optimized performance for their individual boards.
- Differential cycle-to-cycle jitter <50ps
- PCIe Gen1/Gen2/Gen3/Gen4/Gen5 CC compliant
- PCIe Gen 2 and 3 SRiS and SRnS compliant
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Function | Buffer |
| Number of Outputs | 2 |
| Output Type(s) | HCSL |
| Maximum Output Frequency (MHz) | 100, 125, 133.33, 156.25 |
| Additive Jitter (ps) | 0.05 |
| Supply Voltage (V) | 3.3 |
| Input Type(s) | HCSL |
| Skew (PS) | 50 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
