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PI6LC4840

CMOS & LVDS Ethernet Clock Generator

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Product Description

The PI6LC4840 is an LC VCO based low phase noise design in- tended for the most demanding Ethernet applications. Common Ethernet frequencies of 25MHz and 125MHz are supported, with the 125Mhz having both LVDS and LVCMOS outputs for maximum flexibility. One 25Mhz LVCMOS non-PLL output is also available. 

Features

  • 3.3V supply voltage ± 5% Î Three banks of outputs:
       - Bank A: 3 25/50MHz pin selectable LVCMOS outputs
       - Bank B: 3 125MHz LVCMOS outputs
       - Bank C: 3 125MHz LVDS outputs
  • 1 25MHz LVCMOS reference clock output (no PLL)
  • 25MHz crystal input (SaRonix-eCera P/N FL2500029)
  • Low 1ps max 12k-20MHz integrated phase noise design (for 125MHz CMOS and LVDS outputs)
  • Industrial temperature -40°C to 85°C
  • Package (Pb-free & Green)

       - 32-contact 5x5mm TQFN (ZH) 

Product Specifications

Product Parameters

Compliance (Only Automotive(Q) supports PPAP) Standard
Supply Voltage (V) 3.3
Additive Jitter (ps) 0.45
Skew (PS) 0
Maximum Output Frequency (MHz) 1x 25 MHz, 3x 25/50 MHz, 3x 125 MHz, 3x 125MHz
Input Type(s) Crystal
Output Type(s) LVCMOS, LVDS
Number of Outputs 10
Ambient or Junction Temperature (°C) -40 to 85
Supported Frequencies (MHz) 125, 50, 25

Technical Documents

Recommended Soldering Techniques

TN1.pdf

Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents

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Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN # Issue Date Implementation Date Subject
PCN-2698 2024-10-09 2025-04-09 Product End of Life (EOL)
PCN-2520 2021-05-27 2021-08-27 Qualified Additional Bump Site and Assembly/Test (A/T) Sites
PCN-2328 2018-04-12 2018-10-12 Device End of Life for tray packaging only