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DMP1010UCA4

P-Channel Enhancement Mode MOSFET

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Description

This new generation Lateral MOSFET (LD-MOS) is designed to minimize on-state losses and switch ultra-fast, making it ideal for high-efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(ON) per footprint area.

Feature(s)

  • LD-MOS Technology with the Lowest Figure of Merit:
    • RDS(ON) = 9.9mΩ to Minimize On-State Losses
    • Qg = 7.0nC for Ultra-Fast Switching
  • VGS(TH) = -0.80V typ. for a Low Turn-On Potential
  • CSP with Footprint 1.2mm x 1.2mm
  • Height = 0.35mm for Low Profile
  • ESD Protected Gate
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
  • Halogen and Antimony Free. “Green” Device (Note 3)For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/

Application(s)

  • Battery protections
  • Battery managements
  • Load switches

Product Specifications

Product Parameters

AEC Qualified No
Compliance (Only Automotive(Q) supports PPAP) Standard
Polarity P
ESD Diodes (Y|N) Yes
|VDS| (V) 8 V
|VGS| (±V) 6 ±V
|IDS| @TA = +25°C (A) 10
PD @TA = +25°C (W) 1.75
RDS(ON)Max@ VGS(4.5V)(mΩ) 9.9 mΩ
RDS(ON)Max@ VGS(2.5V)(mΩ) 15 mΩ
RDS(ON)Max@ VGS(1.8V)(mΩ) 40 mΩ
|VGS(TH)| Min (V) 0.4 V
|VGS(TH)| Max (V) 1.05 V
QG Typ @ |VGS| = 4.5V (nC) 7 nC
CISS Typ (pF) 699 pF
CISS Condition @|VDS| (V) 4 V

Related Content

Packages

Technical Documents

SPICE Model

Recommended Soldering Techniques

TN1.pdf