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DMN1004UFV

12V N-CHANNEL ENHANCEMENT MODE MOSFET

Datasheet

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Description

This MOSFET is designed to minimize the on-state resistance (R_DS(ON)), yet maintain superior switching performance, making it ideal for high efficiency power management applications.

Feature(s)

Low R_DS(ON) – Ensures On-State Losses are Minimized
Small Form Factor Thermally Efficient Package Enables Higher Density End Products
Occupies just 33% of the Board Area Occupied by SO-8 Enabling Smaller End Product
ESD Protected Gate

Application(s)

Power Management Functions
DC-DC Converters
Battery

Product Specifications

Product Parameters

AEC Qualified	No
Compliance (Only Automotive(Q) supports PPAP)	Standard
Polarity	N
ESD Diodes (Y\|N)	Yes
\|V_DS\| (V)	12 V
\|V_GS\| (±V)	8 ±V
\|I_DS\| @T_C = +25°C (A)	70
P_D @T_A = +25°C (W)	1.9
R_DS(ON)Max@ V_GS(4.5V)(mΩ)	3.8 mΩ
R_DS(ON)Max@ V_GS(2.5V)(mΩ)	5.1 mΩ
\|V_GS(TH)\| Min (V)	0.3 V
\|V_GS(TH)\| Max (V)	1 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	26 nC
Q_G Typ @ \|V_GS\| = 10V (nC)	47 (@8V) nC
C_ISS Typ (pF)	2385 pF
C_ISS Condition @\|V_DS\| (V)	6 V

Technical Documents

SPICE Model

DMN1004UFV.spice.txt

Recommended Soldering Techniques

TN1.pdf

Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN #	Issue Date	Implementation Date	Subject
PCN-2601	2022-10-28	2023-01-28	Additional Wafer Source for Select Discrete Products
PCN-2425	2019-10-04	2020-01-04	Qualification of Additional Wafer Solderable Front Metal Plating, Back Grinding and Back Metal Process Source, and Additional Wafer Source for Select Products.