COMPLEMENTARY PAIR ENHANCEMENT MODE MOSFET
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This new generation complementary pair enhancement mode MOSFET has been designed to minimize RDS(ON) yet maintain superior switching performance. This device is ideal for use in notebook battery power management and load switch.
AEC Qualified | Yes |
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Compliance (Only Automotive(Q) supports PPAP) | Standard |
Polarity | N+P |
ESD Diodes (Y|N) | No |
|VDS| (V) | 12, 20 V |
|VGS| (±V) | 8, 8 ±V |
|IDS| @TA = +25°C (A) | 9.5, 6.8 |
PD @TA = +25°C (W) | 2.3 |
RDS(ON)Max@ VGS(4.5V)(mΩ) | 17, 35 mΩ |
RDS(ON)Max@ VGS(2.5V)(mΩ) | 25, 55 mΩ |
|VGS(TH)| Min (V) | 0.6, 0.6 V |
|VGS(TH)| Max (V) | 1.5, 1.5 V |
QG Typ @ |VGS| = 4.5V (nC) | 15.6, 15.4 nC |
CISS Typ (pF) | 1495, 1745 pF |
CISS Condition @|VDS| (V) | 6, 10 V |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
PCN # | Issue Date | Implementation Date | Subject |
---|---|---|---|
PCN-2495 | 2021-03-31 | 2021-07-01 | Qualification of Additional Assembly & Test Sites and Additional Wafer Back Grinding and Back Metal Process Source for Select Discrete Products |
PCN-2439 | 2019-12-05 | 2020-03-05 | Qualification of "Diodes Technology (Cheng Du) Company Limited" (CAT) as an Additional Assembly & Test Site, Using Gold Bond Wire, and as an Additional Wafer Back Grinding and Back Metal Process Source on Select MOSFET Products |