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DMP1011LFV

P-CHANNEL ENHANCEMENT MODE MOSFET

Datasheet

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Description

This MOSFET is designed to minimize the on-state resistance (R_DS(ON)), yet maintain superior switching performance, making it ideal for high efficiency power management applications.

Feature(s)

Low R_DS(ON) – Ensures On-State Losses Are Minimized
Small Form Factor Thermally Efficient Package Enables Higher Density End Products
Occupies Just 33% Of The Board Area Occupied By SO-8 Enabling Smaller End Product
ESD Protected Up To 3KV
Totally Lead-Free & Fully RoHS Compliant
Halogen and Antimony Free. “Green” Device
Qualified to AEC-Q101 Standards for High Reliability

Application(s)

Backlighting
Power Management Functions
DC-DC Converters

Product Specifications

Product Parameters

AEC Qualified	Yes
Compliance (Only Automotive(Q) supports PPAP)	Standard
Polarity	P
ESD Diodes (Y\|N)	Yes
\|V_DS\| (V)	12 V
\|V_GS\| (±V)	6 ±V
\|I_DS\| @T_A = +25°C (A)	13
\|I_DS\| @T_C = +25°C (A)	19
P_D @T_A = +25°C (W)	1.05
P_D @T_C = +25°C (W)	2.16
R_DS(ON)Max@ V_GS(4.5V)(mΩ)	11.7 mΩ
R_DS(ON)Max@ V_GS(2.5V)(mΩ)	18.6 mΩ
\|V_GS(TH)\| Min (V)	0.6 V
\|V_GS(TH)\| Max (V)	1.2 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	7.1 nC
C_ISS Typ (pF)	913 pF
C_ISS Condition @\|V_DS\| (V)	6 V

Technical Documents

SPICE Model

DMP1011LFV.spice.txt

Recommended Soldering Techniques

TN1.pdf

Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN #	Issue Date	Implementation Date	Subject
PCN-2425	2019-10-04	2020-01-04	Qualification of Additional Wafer Solderable Front Metal Plating, Back Grinding and Back Metal Process Source, and Additional Wafer Source for Select Products.