Back to MOSFET Master Table

DMP2101UCP9

DUAL P-CHANNEL ENHANCEMENT MODE MOSFET

Datasheet

Contact Sales

Description

This new generation MOSFET is designed to minimize the on-state resistance (R_D1D2(ON)) yet maintain superior switching performance, making it ideal for high-efficiency power-management applications.

Feature(s)

LD-MOS Technology with the Lowest Figure of Merit:
- R_D1D2(ON)= 63mΩ to Minimize On-State Losses
- Q_g = 3.2nC for Ultra-Fast Switching
V_GS(TH)= -0.74V typ for a Low Turn-On Potential
CSP with Footprint 1.5mm × 1.5mm
Height = 0.32mm for Low Profile
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/

Application(s)

Battery management
Load switches
Battery protections

Product Specifications

Product Parameters

AEC Qualified	No
Compliance (Only Automotive(Q) supports PPAP)	Standard
Polarity	P
ESD Diodes (Y\|N)	Yes
\|V_DS\| (V)	20 V
\|V_GS\| (±V)	6 ±V
\|I_DS\| @T_A = +25°C (A)	3.1
P_D @T_A = +25°C (W)	1.47
R_DS(ON)Max@ V_GS(4.5V)(mΩ)	100 mΩ
R_DS(ON)Max@ V_GS(2.5V)(mΩ)	130 mΩ
R_DS(ON)Max@ V_GS(1.8V)(mΩ)	175 mΩ
\|V_GS(TH)\| Min (V)	0.4 V
\|V_GS(TH)\| Max (V)	0.9 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	3.2 nC
C_ISS Typ (pF)	392 pF
C_ISS Condition @\|V_DS\| (V)	10 V

Technical Documents

SPICE Model

DMP2101UCP9.spice.txt

Recommended Soldering Techniques

TN1.pdf