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DMP6023LFG

60V P-CHANNEL ENHANCEMENT MODE MOSFET

Datasheet

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Description

This MOSFET has been designed to minimize the on-state resistance (RDS(ON)) and yet maintain superior switching performance, making it ideal for high efficiency power management applications.

Feature(s)

Low RDS(ON) – ensures on state losses are minimized
Small form factor thermally efficient package enables higher density end products
Occupies just 33% of the board area occupied by SO-8 enabling smaller end product

Application(s)

Backlighting
Power Management Functions
DC-DC Converters

Product Specifications

Product Parameters

AEC Qualified	Yes
Compliance (Only Automotive(Q) supports PPAP)	Standard
Polarity	P
ESD Diodes (Y\|N)	No
\|V_DS\| (V)	60 V
\|V_GS\| (±V)	20 ±V
\|I_DS\| @T_A = +25°C (A)	7.7
P_D @T_A = +25°C (W)	2.1
R_DS(ON)Max@ V_GS(10V)(mΩ)	25 mΩ
R_DS(ON)Max@ V_GS(4.5V)(mΩ)	33 mΩ
\|V_GS(TH)\| Max (V)	3 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	26.5 nC
Q_G Typ @ \|V_GS\| = 10V (nC)	53.1 nC
C_ISS Typ (pF)	2569 pF
C_ISS Condition @\|V_DS\| (V)	30 V

Technical Documents

SPICE Model

DMP6023LFG.spice.txt

Recommended Soldering Techniques

TN1.pdf

Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN #	Issue Date	Implementation Date	Subject
PCN-2495	2021-03-31	2021-07-01	Qualification of Additional Assembly & Test Sites and Additional Wafer Back Grinding and Back Metal Process Source for Select Discrete Products
PCN-2456	2020-05-29	2020-08-29	Qualification of Internal "Diodes Technology (Cheng Du) Company Limited" (CAT) as an Additional Assembly & Test Site Using Copper or Palladium Coated Copper Bond Wire with Standardization of Assembly Bill of Materials, Or as an Additional Wafer Plating, Back Grinding and Back Metal Process Source, and Qualification of Additional Wafer Source for Select Discrete Products.