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DMT6009LSS

60V N-CHANNEL ENHANCEMENT MODE MOSFET

Datasheet

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Description

This new generation MOSFET is designed to minimize the on-state resistance (R_DS(ON)), yet maintain superior switching performance, making it ideal for high efficiency power management applications.

Feature(s)

100% Unclamped Inductive Switch (UIS) Test in Production
High Conversion Efficiency
Low R_DS(ON) – Ensures On-State Losses Are Minimized
Excellent Q_gd x R_DS(ON) Product (FOM)
Advanced Technology for DC-DC Converters

Application(s)

Power Management Functions
DC-DC Converters
Backlighting

Product Specifications

Product Parameters

AEC Qualified	No
Compliance (Only Automotive(Q) supports PPAP)	Standard
Polarity	N
ESD Diodes (Y\|N)	No
\|V_DS\| (V)	60 V
\|V_GS\| (±V)	20 ±V
\|I_DS\| @T_A = +25°C (A)	10.8
P_D @T_A = +25°C (W)	1.6
R_DS(ON)Max@ V_GS(10V)(mΩ)	9.5 mΩ
R_DS(ON)Max@ V_GS(4.5V)(mΩ)	12 mΩ
\|V_GS(TH)\| Max (V)	2 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	15.6 nC
Q_G Typ @ \|V_GS\| = 10V (nC)	33.5 nC
C_ISS Typ (pF)	1925 pF
C_ISS Condition @\|V_DS\| (V)	30 V

Technical Documents

SPICE Model

DMT6009LSS.spice.txt

Recommended Soldering Techniques

TN1.pdf

Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN #	Issue Date	Implementation Date	Subject
PCN-2403	2019-03-25	2019-06-19	Qualification of Additional Wafer Solderable Front Metal Plating, Back Grinding and Back Metal Process Source, Additional Wafer Source, or Additional Assembly and Test site for Select Products.