PI2DDR321 is a 1 bit 2 to 1 GDDR5 mux operating at 1.35V/1.5V supply and is designed for GDDR5 memory bus with speeds up to 5 Gbps. It is used to gate the clock signal only when bus is active thus saving power.
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
PCN # | Issue Date | Implementation Date | Subject |
---|---|---|---|
PCN-2602 | 2023-01-31 | 2023-07-31 | Device End of Life (EOL) |