NRND = Not Recommended for New Design
3.3V, Low Skew Differential to LVDS Fanout Buffer
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The PI6C48543 is a high-performance low-skew LVDS fanout buffer. PI6C48543 features two selectable differential inputs and translates to four LVDS outputs. The inputs can also be confi gured to single-ended with external resistor bias circuit. The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL or CML signals. The outputs are synchronized with input clock during asynchronous assertion/deassertion of CLK_EN pin. PI6C48543 is ideal for differential to LVDS translations and/or LVDS clock distribution. Typical clock translation and distribution applications are datacommunications and telecommunications.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Function | Buffer |
| Number of Outputs | 4 |
| Output Type(s) | LVDS |
| Maximum Output Frequency (MHz) | 800 |
| Additive Jitter (ps) | 0.05 |
| Supply Voltage (V) | 3.3 |
| Input Type(s) | Differential |
| Skew (ps) | 40 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2428 | 2019-11-12 | 2020-02-12 | Assembly & Test Site Porting from OSE to Greatek |
