LVPECL Clock Buffer with "divide by 2" feature
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PI6C4911504D2 is a high performance differential buffer with divide by 2 capability. There are also 2 selectable muxed inputs. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations with a change from the input frequency.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Function | Buffer |
| Number of Outputs | 4 |
| Output Type(s) | LVPECL |
| Maximum Output Frequency (MHz) | 650 |
| Additive Jitter (ps) | 0.03 |
| Supply Voltage (V) | 2.5, 3.3 |
| Input Type(s) | LVCMOS, Differential |
| Skew (ps) | 65 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
