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W-QFN5050-32.pngVery Low Power 4-Output PCIe Clock Buffer With On-Chip Termination
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The PI6CB33402 is a 4-output very low power PCIe® Gen 1/Gen 2/Gen 3/Gen 4/Gen 5 clock buffer. It takes a reference input to fanout four 100MHz low power differential HCSL outputs with on-chip terminations. The on-chip termination can save 16 external resistors and make layout easier. Individual OE pin for each output provides easier power management.
It uses Diodes proprietary PLL design to achieve very low jitter that meets PCIe Gen 1/Gen 2/Gen 3/Gen 4/Gen 5 requirements. Other than PCIe 100MHz support, this device also supports Ethernet application with 50MHz, 125MHz and 133.33MHz via SMBus. It provides various options such as different slew rate and amplitude through SMBUS so that users can configure the device easily to get the optimized performance for their individual boards.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Function | Buffer |
| Number of Outputs | 4 |
| Output Type(s) | HCSL |
| Maximum Output Frequency (MHz) | 100, 125, 133.33, 156.25 |
| Additive Jitter (ps) | 0.05 |
| Supply Voltage (V) | 3.3 |
| Input Type(s) | HCSL |
| Skew (PS) | 50 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2520 | 2021-05-27 | 2021-08-27 | Qualified Additional Bump Site and Assembly/Test (A/T) Sites |
